2.4.1 Design

The SHARAD instrument is functionally composed by two building blocks:

• The transceiver, composed by two units (named RDS and TFE) located in the SHARAD Electronic Box (SEB)

• The antenna (10 m foldable dipole)
  

The RDS implements both digital (including digital chirp generation) functions in the DES and
the analogue, receiving functions in the RX.
A functional block diagram is provided in fig 2.3.1-1.

Figure 2.4-1: SHARAD Block Diagram.

2.4.1.1 Tx/Rx functions

The transmitting chain is composed by a digital chirp generator (DCG), located in the RDS/DES, that generates the transmitted chirp directly at RF (20 MHz +/- 5 MHz) using a stepped-phase Direct Digital Synthesizer (DDS).

This approach has been preferred versus the more flexible Memory ReadOut approach for its lower complexity. Compensation for hardware distortions (which can be introduced in the transmitted signal using an MRO approach) shall be (due to the tight distortions requirements) implemented on ground on the received data anyway, making the Memory ReadOut flexibility advantage useless. The DDS approach should also allow to easy change the transmitted pulse initial phase, which can be exploited for range-rate compensation.

The signal from the Digital Chirp Generator is boosted to suitable power level in the TFE, by means of a class C power amplifier.

The TFE contains also:

• the balun to provide a balanced feed to the antenna;

• the matching network required to ensure the optimum power transfer to/from the antenna;

• the T/R switch to provide duplexing between Tx and Rx functions.

The power amplifier works on 50 Ohm impedance and feed the T/R switch (implemented with an high power MOSFET). A low-pass, multicell matching network, followed by a balun match the 50 Ohm impedance seen on the T/R side to the high impedance, frequency dependant, balanced impedance of the antenna.

The antenna is a dipole, 10 m long, realised using 2 flexible dielectric tubes (one each arm) containing a wire which is, in fact, the effective antenna element.

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The tubes are folded and tied together during launch and cruise and deployed by release of the tie-down brackets.

On receiving, the signal from the antenna follow the reverse path until the T/R, which route the signal to the TFE Rx output, connected to the receiver.

The receiver performs the following tasks:

• signal amplification

• bandpass filtering

• gain control (open loop, under control of the DES)

• analogue-to-digital conversion

• The A/D converter, operating at the RF frequency (after up-conversion, if processing and down-conversion) performs an undersampling of the signal, acquiring, during the receive window, at a rate of 26.67 Msamples/sec, with a resolution of 8 bits. The sampling frequency has been selected in order to:
• allow unambiguous sampling of the received signal over the range 15-25 MHz

• simplify extraction of baseband I/Q components for later processing 8both on-board and on-ground)

The digitised data are then transferred to the DES section of the RDS, where they are buffered in a FIFO before being fed to the FPGA which is in charge of echo presumming and pre-formatting. The surface tracking function is software implemented by the DES Supervisor, which also schedule all the activities related to radar operations. The digitised and processed data are then packetised and sent to the Spacecraft.

2.4.1.2 Instrument Control function

The control of the instrument is also performed by the DES Supervisor (a TSC21020 DSP), by receiving Telecommands sent by the S/C and processing them according to its operational state. The DES Supervisor activities are monitored by means of Housekeeping Telemetries. Time-keeping services are also managed and synchronised to S/C OBT.

While Telecommands are received by the S/C C&DH (Command and Data Handling) computer, Telemetries are sent to the S/C SSR (Solid State Recorder) together with Science Data packets. S/C monitoring of the instrument is accomplished through 4 discrete TM signals, which provide status information to the S/C FSW (Flight Software). The S/C C&DH can disable activation of SHARAD TFE by means of a dedicated discrete TC.

2.4.2 Operations

SHARAD is designed to be kept, when not operating any of the science modes, in a minimum power state (STAND-BY) with only the digital electronics powered. In this state the instrument is able to receive commands from the S/C.

During the operational science modes, SHARAD does not respond to S/C commands and operates according to a pre-programmed sequence recorded in the Operation Sequence Table (OST), loaded during the STAND-BY mode, and triggered by an Enable OST command.

During these programmed operations, other two pre-loaded tables are used by SHARAD: the Parameter Table (PT) containg information about surface topography and required slope compensation, and the Orbital Data Table (ODT), containing predicted orbital data like

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spacecraft altitude and radial velocity. Also these tables are loaded while in STAND-BY state.

After completion of the OST sequence, SHARAD returns in STAND-BY state and is ready to be programmed for another science pass. SHARAD can be programmed only for one science pass at each time.

In case of anomalies, the instrument, as well as a science pass sequence, can be suddenly switched off without any concern for the instrument.

3.2.1 Digital Equipment Section

The Digital Electronics Section (DES) is the heart of SHARAD and concentrates many functions of the instrument, including command and control, low-power radar pulses generation, science data processing and formatting, timing. The DES provides all the hardware and software components in order to enable SHARAD operations. These components are used to perform the following functionalities:

• command and control capability (by way of S/C’s C&DH);

• command and control capability of other SHARAD’s units;

• formatting of Science Data and their transfer as Telemetry to the S/C’s SSR;

• generation of Housekeeping Telemetry and its transfer to the S/C’s SSR;

• generation of the radar chirp signal;

• processing of radar raw data;

• provision of a high-stability oscillator and generation of timekeeping and synchronisation signals for all SHARAD’s units;

• power conditioning and distribution to the other SHARAD’s units.

The DES is based on a modular design. The Receiver Section (RX) shares DES’ same mechanical form factor and is joined to the DES to is also implemented as a self-standing module within the DES architecture.

The following picture shows DES functional architecture from a top-level design viewpoint:

TFE_PWR_ON_OFF DES_PWR_MAIN

TFE_PWR DES_PWR_RED

TFE_CHIRP DES_PPS

TFE_GATE

DES_CMD

TFE_SYNCH TFE_TXRX DES_CMD_SELECT

RX_GATE

DES_TC_1

RX_ADC_SOC RX_ATTSEL

DES_TM_1
DES_TM_2

TFE_TEMP TFE_LEVEL

DES_TM_3 TFE_BUS_CUR

DES_TM_4 RX_TEMP Int. Monitors

DES_SD RX_DATA

Figure 3.2.1-1: DES Functional Architecture

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SHARAD’s DES is constituted by the following items (see figure 3.2.1-2):

• DSP Module

• Service Module

• Digital Chirp Generator (DCG) Module

• Harness

• Mechanics

The DSP Module is constituted by the Command & Control Board and the Slave Board,
which are mounted on the same mechanical frame.
The Service Module is constituted by the Timing Board and the DC/DC Converter Board,

which are mounted on the same mechanical frame.

The Digital Chirp Generator Module is constituted by the DCG board enclosed in its own
mechanical frame.
The boards are connected one to the other through the DES internal harness, which allows

also the connections with the SHARAD Receiver (once mechanically joined to the DES to

form the RDS).
DES block schematic is shown in Figure 3.2.1-3 while overall interconnections are depicted
in Figure 3.2.1-3.

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Figure 3.2.1-2: DES mechanical composition.

Figure 3.2.1-3: DES Block Schematic.

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TM_

N TC_TM_TIC TC_ABSEL

RR N SYSBUS

JTAG

Figure 3.2.1-4: DES boards interconnections.

MOD:PRC-Q3-05-002/R-b Ed. B

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3.2.1.1 DC/DC Converter Board

SHARAD power distribution is managed by the DC/DC Converter Board, which also provides all the required supply voltages (according to the block schematic in Figure 3.2.1-4).

Figure 3.2.1-5: DES Power Distribution

The DES and the RX are powered by the same DC/DC converter.

The RX DC/DC converter can be switched ON with a bilevel signal under SW control.

The TFE DC/DC converter is located in the TFE, and can be switched ON/OFF under SW control through an optocoupled interface. The 28V for the TFE is the OR of the nominal and the redundant lines.

The DES and RX DC/DC converter is a free running one at 131KHz +-10% (which bears no correlation with any of SHARAd’s PRF values) and provides synchronisation to the TFE DC/DC converter (which is slaved to DES DC/DC converter’s frequency).

.

Figure 3.2.1-6: DC/DC Converter Board Block schematic

MOD:PRC-Q3-05-002/R-b Ed. B

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3.2.1.2 Command & Control Board

The command and control board design is derived from the one of MARSIS and is based on a ATMEL’s Digital Signal Processor TSC21020F operating at 20 MHz. CPU clock is derived from the 80 MHz Master Oscillator on the Timing Board.

The DSP can access contemporarily two different memory buses:

• The Program memory bus, where two different banks of memories are mounted

• The Data memory bus, on which one memory bank and one FPGA are mounted The Program memory is constituted by:

• 512K words on 48 bits Static RAM accessed at 0 wait states, for fast program execution;

• 128K words on 48 bits EEPROM accessed at 7 waits states, for code storage.

The first page of the EEPROM is write-protected, so that is appears as a PROM to the SW. Write protection is removable only when the external emulator is connected to the DES via the JTAG connector (J13), used also for program loading into EEPROM.

The data memory is constituted by a 512K 32-bit words SRAM bank, accessible at 0 wait

states, on the first segment of data bus.
The FPGA implements all the functionalities that allow the processor to control the DES.
These include:

• System Bus access (corresponding to 7 waits states for the DSP)
  

• On-Board Time management
  

• Interrupt controller
  

• Watchdog
  

• Reset circuitry
  

• PRI counter
  

• EEPROM protection
  

• DCG serial interface (memory load type)
  The System Bus is a dedicated I/O bus (not a CPU bus) that connects all DES boards, but
  the DC/DC Converter one and the DCG. It allows to transfer 16 bit data every 350ns.
  

Addressing capability is 8k addresses and 2 other bits are decoded on the board to select 4 other banks on the bus. The HW Watchdog present on the board is periodically reset by SW. If 30 seconds elapse

without reset, then the Watchdog will fire issuing a reset pulse to the DSP and to the other
boards. If the 30 seconds timeout expires again (after the first timeout), then the Watchdog
definitely resets the system putting it into a blocked state, and a Power Off – Power On cycle
is required to restart the instrument.

3.2.1.3 Timing Board
The Timing Board implements three main functions:

• sequencing of the RADAR
  

• acquiring of the analogue monitors telemetries
  

• providing the optocoupled interfaces for the discretes TM and TC.
  The Timing Board design is built around a FPGA that provides the following resources:
  

• the system bus interface;
  

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• the RADAR sequencer programming registers;

• the analogue monitoring chain sequencer and storage;

• the I/O registers for the optocouplers.

The Timing Board hosts SHARAD’s Master Oscillator, which provides the 80MHz clock to the system with the following characteristics.

Frequency	80MHz
Initial Accuracy	Settable to 0.1 ppm via external fixed resistor
Temperature stability	±1 ppm over –20°C to +70°C including hysteresis and perturbations.
Short-term stability (10s)	0.001 ppm, under constant and static conditions
Long term stability (30min)	0.01 ppm, under constant and static conditions
Frequency vs. supply	±0.5 ppm for a ±5% change
Aging	<1.5 ppm first year <1 ppm per year average thereafter

The FPGA derives all other needed clocks to sequence the radar with the following clock

distribution concept:
	DCG Base
	Div 3		Div 4		20 MHz DSP Clk
	Sequencer / 4	DCG			26,6667 MHz SDI Clk 26,6667 MHz ADC SoC DCG Trg +/- 150 ns
		Div 9520 Div 9947 Div 8600		Div 2	PRF (670.22, 700.28, 775.19 Hz) Half PRF (335.11, 350.14, 387,6 Hz)

Figure 3.2.1-7: Timing Board Clock Distribution Concept

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3.2.1.4 Slave Board

The Slave Board implements three main functions:

• reception and buffering of telecommands from the C&DH;

• buffering transmission of telemetries to the SSR;

• echo data buffering and processing (presumming and compression, followed by packet preparation).

• The Slave board is built around a FPGA which interfaces:
• a FIFO memory (8k x 8bit) written by the Timing board with the data coming from the receiver;

• a Dual Port memory (4 IC 8k x 16bit each) which can be accessed by the system bus

• (i.e. the DSP) on the other port
• a pair of LVDS receivers, that interface with the C&DH

• a pair of LVDS drivers that interface with the SSR

The A/B Side Select optocoupled interface is also implemented on this board to select either the nominal or the redundant Command interface. The SSR Telemetry interface is, on the other hand, hot redundant (both drivers are always active and generating data).

The optocoupled Time_Tic signal is buffered to TTL levels and sent to the C&C for OBT management.

Commands received by the C&DH are sampled as 32 bits wide words. Each word generates an interrupt to the DSP, which in turn has 62 msec to fetch the data.

Transmission of telemetries to the SSR is a process started by the DSP and automatically managed by the Slave Board, which makes a available up to 32K 16-bit words as telemetry buffer (in the DP memory). Compression is implemented while transmitting the data field of a science packet. Packet checksum is computed on the fly, and added to the packet while transmitting.

Processing mainly concerns the Pre-summing function which is implemented by storing interim pre-summed results in the DP memory.

Data exchanges with the C&C Board foresee that Tracking algorithm data are accessed at a relatively slow rate in order to avoid DP memory conflicts.

The two packet buffers shown in next figure are alternatively used in a ping-pong fashion. The DSP fills in the header (time tag) and auxiliary data before transmission to the SSR.

Figure 3.2.1-8: C&C and Slave science data exchanges. The DP memory has a single, separate, buffer for HK Telemetry packets.

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3.2.1.5 Digital Chirp Generator

The DCG is a module that synthesizes the Chirp signals in the Digital Electronic Section (DES). It has been designed using the Direct Digital Synthesis Technique, which consists in the generation of discrete samples of a sinewave and in the successive reconstruction at analog level.

A custom Numerical Controlled Oscillator has been employed to implement this technique.

The NCO allows obtaining both surface area occupation and power consumption savings. The DCG is a programmable signal generator. This characteristic permits to Shallow Radar to achieve an high flexibility and adaptability of use during the mission

The Digital Chirp Generator is built around a Numerical Controlled Oscillator (NCO). The main functional blocks of this architecture (see next figure) are:

• Command Interface

• ASIC:

1. o Chirp Parameter register

2. o NCO

• Look-up Table Prom

• Timing & Control Logic

• Digital to Analog Converter

• Low Pass Filter

• Output Amplifier

• Interface (for DCG signals and for test points)

ML_DATA_VALID

ML_DATA ML_CLOCK

MLCmd

+ 5V DCG_POWER_DIG L. R.

EN_DAC_DATA_TEST

+ 5V

Serial to Parallel WRn_TEST

-5V I/F

DCG_POWER_AN +12V CKDIV4_TEST

COMMAND INTERFACE

START_CHIRP_TEST

TRIGGER_TEST CK80MHZ_TEST

Power Divider

Start
Freq.

CHIRP PARAMETER REGISTERS

ASIC

10

Sel BitsDCG_TRIGGER TIMING

NCO

& Chirp

DCG_CLOCK80MHZCONTROL Start LOGIC

Clock

PROM

DCG_RESET

LUT

Power On

DAC

LOW PASS
FILTER

DCG_MONITOR DCG_OUT

DIGITAL CHIRP
GENERATOR CARD

Figure 3.2.1-9: Digital Chirp Generator block schematic.

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The principal tasks in the Chirp Generator are the following:
Command Interface
It allows to receive from DES Supervisor a serial Memory Load Command, through the which

Start Frequency, Phase Compensation, Bandwidth and Pulse Duration of the chirp signal
may be set.
Details about DCG commands and parameters are given in para. 3.4.2.
Timing & Control Logic

It performs all the timing functions required in the DCG.
It synchronizes the Start of the pulse generation with the External Trigger coming from the
DES. It has the task to prevent the clock ambiguities that may cause jitter or indeterminate
pulse starts.

In addition it provides all the specific signals necessary for the correct working of the NCO.
ASIC
The NCO (Numerical Controlled Oscillator) function is implemented on a single fully space

qualified ASIC - developed by ALS in the frame of the activities for the SAR 2000 Program.
The main features of the ALS NCO are listed below:

• Flexibility: all parameters are configurable(start freq,slope,phase comp,duration)

• Frequency Resolution: 32-bits (0.018 Hz @ 80 MHz clock)

• Wide Output Bandwidth: 0 to 32 MHz @ 80 MHz clock

• CW or Chirp Signal Gen.: 10 bit outputs

• Automatic Download of the External Look-up Table Prom content

• µProcessor Compatible input (16 bits BusAddress and 16 bits BusData)

• Low Power Dissipation: 520 mW @ 80 MHz (Core and I/O powered at 3.3V)

• Technology: ATMEL MH1 RT (0.35µm CMOS, Sea of gates, latch up immune, 200+ Krads total dose capability)

3.2.1.6 DES General Data Flow
During scientific processing, DES nominal operation are the following ones:

1. At the beginning of the operating mode, the SW knows from the OST line which is the PRF that must be programmed in the timing board sequencer, and sets it in the Timing Board registers.

2. The SW also programs the timing sequencer to samples the echo at a given Rxdist (RX Window opening time since PRI trigger).

3. The SW finally programs the Slave Board about where to store the results and prepares the headers of the scientific packet in the active packet buffer.

4. The Timing Board issues the PRF signal.

5. The PRF signal forces, in the C&C Board, the SW to program DCG, RX and TX parameters.

6. The Timing Board fires the DCG (already programmed with the correct phase) with the trigger.

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1. After Rxdist interval has elapsed, the Timing Board commands the writing of data samples into the Slave Board FIFO.

2. After 3600 samples are written into the FIFO, the Timing Board triggers the Processing function in the Slave FPGA.

3. When the Processing function ends in the Slave Board a signal is sent to the C&C Board.

4. If the required Pre-summing value has been reached, the SW re-programs the Slave FPGA and triggers it to start Science telemetry transmission of the previously computed data. Otherwise another PRI cycle is programmed and newly sampled data will be summed to the previous ones stored in the DP buffer.

5. The SW keeps track of the PRI to computed the new phase of the DCG and be prepared to respond to the next PRF pulse.

HK telemetry packets are generated in an asynchronous way with respect to the PRI. They are prepared in the HK packet buffer of the Slave DP memory by the SW. HK packets, when ready, are transmitted between two scientific packets, when the opportunity occurs.

3.2.2 Receiver Section

From an architectural point of view, SHARAD’s receiver has been designed without the need for frequency-conversion, the receiver’s F.E. performs a band-pass filtering function, while the received signal is amplified to a level enough to A/D convert.

The SHARAD’s receiver is based on band-pass sampling technique, so doing the sampling rate can be much lower than those required by sampling at two or more times the highest frequency content of the band-pass signal. In fact, to satisfy the Nyquist’s theorem the sampling rate must be at least twice the bandwidth of interest, not necessarily twice the highest frequency component.

The choice of direct digitization of the RF input signal has, for this application, several advantages w.r.t. frequency-conversion configuration receiver.

Firstly, the most obvious reason regards the conversion mixer, which is used no longer. Secondly, we don’t need a built-in LO for conversion any more.

The SHARAD’s receiver unit, from a mechanical point of view, consists of a double-sided module that houses all the circuitry.

By looking at fig 3.2.2-1 (Receiver Electrical Block Diagram) a brief overview of the unit can be given.

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+10.5 V+10.5 V +10.5 V +5 V -5.5 V

INPUT
SWITCH

+10.5 V Vcntrl

PRESELECT CHANNEL CHANNEL

FILTER FILTER FILTER1st LNA 2nd LNA

AMP_1 AMP_2

AMP_3 AGC ATT_1RF IN

20 MHz

PAD_1 High_Pass Low_PassPAD_2

Section Section

PAD_3 RX_ATT-SEL -5.5V

GAIN BLOCK # 1 GAIN BLOCK # 2 TEMP. COMP.

+5V

GAIN & ATT. BLOCK # 1 RX_GATE

GAIN & ATT. BLOCK # 2

OUT BUFFERS

A/D CONVERTERGAIN BLOCK # 3

AMP_5 AMP_6AMP_4 AGC ATT_2 DATA

A/D

OUTPUT

INPUT
VOLTAGES

RX_ATT-SEL

PAD_4 +10.5 V+5 V DIG

±3% +10.5 V +5 V

-5.5 V

+5 V ANLG
±3%

+5 V DIG

ADC_SoC -5.5 V ANLG

±3%

±3%

TEMPERATURE			Vcontrol
+Vcc
SERIES
+12.5 V		CONTROL NETWORK
±5%	REGULATOR
		+10.5 V
		RX_TEMP_TLM
		TEMP.
		TELEMETRY
		Figure 3.2.2-1: RX Section Block Schematic

The incoming signal, after having been filtered by a 5-pole Pre-select Low Pass Filter to cope with the electromagnetic environment, is sent to the LNA. The LNA consists of two cascaded SMD devices, where the the first stage is optimized for noise figure, while the second one is optimized for gain. The LNA is blanked, by the RX_gate CMD, which enables the Input Switch during transmission to route the input signal to a dummy load rather than to receiver’s input.

The signal enters the Channel Band-shape Filter (Anti-aliasing Filter), which is split into two sections: High Pass and Low Pass section with a couple of amplifiers in between. This has been done to cope with the wide filter fractional bandwidth (50%) w.r.t. the 20 MHz center frequency. So doing we designed two filters: a 7-pole Cebicef HPF and an 11-pole Cebicef LPF. These filters are manufactured by using both wire-wound inductor (on a magnetic core) and ceramic SMD capacitors. A couple of SMD amplifiers is placed between the two filter sections. They provide about 13 dB gain along with 22 dB of isolation for decoupling the filter sections.

The signal emerging from the LPF is sent to a Temperature Compensating Network which compensates for the overall gain variation over –20°C to +65°C temperature range. It is based on a SMD device using a Pi configuration of PIN diodes. In fact, the PIN diode can be used as a current controlled variable resistor. The Pi configuration provides a very good match and very flat attenuation over an extremely wide band. Doing so, we can compensate for gain variation due to temperature up to ± 3 dB.

Going along the receiving chain we find two Gain & Attenuator Blocks, whose task is to amplify the signal and control the overall receiver gain. These two blocks rely on SMD amplifiers and on two 4-bit digital attenuators (1-dB step), which provide up to 30 dB of attenuation.

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A couple of amplifiers provide the A/D Converter with a suitable signal for full scale. Moreover, they have a high third order intercept point.

The ADC converts the signal to digital form working at sampling rate of 26.6 MHz.

The AD 9042 is a high speed (41 MSPS min sample rate), high performance, low power monolithic 12-bit ADC (for SHARAD Receiver we need 8 bits only). All necessary functions, including track and hold and reference are included on chip to provide a complete conversion solution. This device has been specifically designed for communications systems, which must digitize a wide signal bandwidth.

Finally, after having been buffered the digital data are sent to User.

Up to now we have described the receiver chain in terms of signal flow, however the receiver unit relies on three other circuits as well. Namely, they are: the series regulator, the temperature compensation control network and the telemetry circuit.

The series regulator acts as an interface between the +12.5 V external power supply line, providing the RF circuits with a filtered and regulated voltage.

The temperature compensation control network delivers to the PIN diode voltage controlled attenuator a voltage proportional to temperature. It consists of two sections: the amplifying section and the linearizing section. As a temperature sensor a monolithic transducer has been used, which provides a linear thermal voltage. Since the attenuation law of the thermal compensating attenuator departs significantly from a linear function, we have to linearize its characteristic by using non-linearity (diode breakpoints) in the feedback path of an Op. Amp.

The telemetry circuit provides a voltage proportional to the Receiver Unit temperature. It uses a well-proven temperature transducer that produces an output current proportional to absolute temperature (1mA/K).

3.2.3 Transmitter/Front-End Section

The Transmitter & Front End Unit (TFE) is a self-standing equipment, devoted to amplify the low level chirp signals coming from the DES unit and to couple them to the dipole antenna; the unit provides also for time division duplexing function, sharing the antenna between the transmitter and the receiver path.

The TFE includes internal DC/DC converter to supply all internal circuitry and to provide galvanic isolation from the power bus; the power supply assures high peak energy over the pulse duration while preventing both from excessive current transients on the main bus and from ripple on the secondary voltage rails.

The main feature of the TFE is the capability to handle wide bandwidth frequency modulated pulsed signals (15 �25 MHz) maintaining as low amplitude/phase distortions over the pulse width as possible (consider that the antenna highly mismatched load causes significant amplitude and phase ripples over the useful bandwidth); nominal operation foresees 85 msec duration pulses with 700 Hz repetition frequency.

A TT&C section interfaces the DES unit, exchanging commands and telemetries; transmitted power level, main bus current and internal temperature are provided as analogue telemetry outputs.

The TFE performances, especially the output power, are very dependent on the impedance characteristics of the antenna which represents the output load of the equipment: a dummy load reproducing the antenna has been designed and implemented for testing purposes; all tuning and characterization activities on the TFE equipment are indeed carried out by GA with the TFE terminated on this antenna simulator.

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The TFE is supplied by a 21 to 36V unregulated bus with the provision for external synchronization (both free running and synchronized operation is foreseen).

A functional block diagram for the TFE equipment is presented in figure 3.2.3-1, while figure 3.2.3-2 shows the unit’s power interface.

TLC/TLM signals

(25 pin female connector)

DC + TT&C

Main Bus
21‚36 V

+28V TT&C

DC/DC _+12V & power switch

(9 pin

converter driver +5V

male connector) -12V

Capacitor filter Forward/reverse coax cable

Chirp Input bias to/from

TNC

15-25 MHz balun

connector

0 dBm

(SMA female)

50 W

Low level amp

Power amp DuplexerTemp

switches TNC connector

Peak Power sense

RF section

BALUN

to/from antenna 2xTNC female

to Receiver Unit

RF test point

(SMA female)

(SMA female)

Figure 3.2.3-1: Transmitter & Front-End Block Schematic. Figure 3.2.3-2: Transmitter & Front-End Power Interface.

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3.2.4 Antenna

SHARAD’a Antenna is a 10 m dipole made of two 5 m foldable tubes, which, in stowed configuration, are kept in place by a system of cradles and, when released, will self-deploy thanks to its elastic properties.

Electrically, the Antenna is fed at the centre, interfacing the SEB by means of two wires (one for each dipole). The connection wires together form a balanced connection line. The line itself has no controlled impedance, (the antenna not having any matching network) and the load seen on the TFE side is therefore frequency dependant (thus requiring a dedicated matching network within the TFE).

The connection cables interface the TFE with 2 TNC connectors.

The Antenna includes also its release mechanism (two solenoid controlled actuators to release the right and left dipoles). During deployment operations, heaters installed on the Spacecraft panel will heat antenna cradle hinges in order to keep the actuator mechanism within a suitable temperature range.

3.3.1 Electrical Interfaces

The following diagram summarizes all SHARAD electrical interfaces.

TFE

RX

SEB

SEB_TEMP_RDS 2

SEB_TEMP_TFE 2

RX_RF

Figure 3.3.1-1: SHARAD Interfaces.

From the grounding viewpoint, SHARAD follows the Distributed Single Point Ground (DSPG) approach, i.e., it is forbidden to use the structure ground as an intentional return path.

For this reason, all the interface to the S/C and between RDS and TFE (interface internal to RDS, i.e. DES <-> Rx are excluded, being part of the same box) are differential in nature, while the DC /DC converters in RDS and TFE are isolated on the primary side (grounded on S/C side only).

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A sketch of the grounding concept is provided in fig 3.3.1-2

TLCs
LVDS

TLMs/DATA

S/C

SHARAD

TFE

THERMISTORS

SELECT

DISCRETE TTL IN (TBC)

Rx

DISCRETE TTL OUT

HEATERS I/F IMPLEMENTATION EXAMPLE

Figure 3.3.1-2: SHARAD Grounding Diagram (concept).

The following discussion partitions the electrical interfaces in Internal ones (shared between instrument units/sections) and External ones, those between SHARAD and S/C.

3.3.1.1 Internal Interfaces – DES to RX RX Data Port A/D converter output interface implementation is depicted in figure 3.3.1-3. Conversion is started on rising edge of “Start of Conversion” (ADC_SoC) signal. This signal

will be continuously active.

Signal name:	RX_DATA
Description:	ADC Digital data output, from Rx to DES
Signal type:	TTL
Number of bits:	8
Data representation:	2’s complement

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Sampling rate:	Through ADC_SoC signal: - 26.67 MHz, nominal - 30 MHz max

Signal name:	ADC_SoC
Description:	ADC Sampling/Latching signal
Signal type:	LVDS
Sampling edge:	Rising (Positive) Edge
Sampling rate:	Rising edge every 37.5 nsec

From Rx analogue section

Rx_DATA port

ADC_SoC

Figure 3.3.1-3: A/D Converter data interface DES Telecommands to Rx

Command name:	RX_GATE
Description:	Control blanking of LNA for receiver protection
Number of bits:	1
Signal Type:	TTL
Control logic:	a) Logic Level Low = Rx ON b) Logic Level High = Rx blanked c) Switching time: <=2 msec

Command name:	ATT_SEL_1
Description:	Select gain control setting of Rx
Number of bits:	4
Signal Type:	TTL
Control logic:	- Inserted attenuation = 0 to15 dB (step 1 dB) - Bit 0=LSB, Bit 3=MSB - plain binary
Notes:	Upstream attenuator (to be inserted first)

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Number of bits:	4
Signal Type:	TTL
Control logic:	- Inserted attenuation = 0 to15 dB (step 1 dB) - Bit 0=LSB, Bit 3=MSB - plain binary
Notes:	Downstream attenuator (to be inserted last)

Rx Telemetry to DES

Telemetry name:	TEMP_TLM
Description:	Hot spot temperature of Rx
Signal Type:	DEA
Range:	-35°C ÷ +70°C

Rx Power

Signal name:	PWR_DIG
Description:	+5 V power line for digital circuits (live line + return)
Signal Type:	Power
Voltage:	+5 V +/- 3% V
Max Current:	260 mA
Ripple:	< 50 mVpp (0 to 50 MHz)

Signal name:	PWR_AN
Description:	Power lines for analogue circuits (3 live lines + common return)
Signal Type:	Power
Voltage:	+ 5 V +/-3% - 5.5V +/-3% +12.5 V +/-5%
Max Current:	30 mA 30 mA 300 mA
Ripple:	< 20 mVpp (0 to 50 MHz)

3.3.1.2 Internal Interfaces – DES to TFE TX Chirp Port

Signal name:	TX Chirp
Description:	Chirp signal from DES to TFE
Connector type:	SMA, female

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Nominal impedance:	50 Ohm
Signal Type:	Linear frequency modulated (chirp) pulse
Centre frequency:	20 MHz
Signal bandwidth:	10 MHz
Pulsewidth:	85 msec, nominal
Power level:	0 dBm (+/- 0.5 dB)

DES Telecommands to TFE

Command name:	PWR_ON_OFF
Description:	Enable/disable DC/DC converter operation
Number of bits:	1
Signal Type:	OPTO
Control logic:	OC ON = TFE ON, OC OFF = TFE OFF

Command name:	TX_RX
Description:	Control the T/R switch and enable the transmitter.
Number of bits:	1
Signal Type:	DIF
Control logic:	LL Low = Tx, LL High = Rx

Command name:	TX_GATE
Description:	Enable Transmission
Number of bits:	1
Signal Type:	DIF
Control logic:	LL 0= ON, LL1=OFF

TFE Telemetry to DES Synchronisation signals

Telemetry name:	TX_LEVEL_TLM
Description:	Analogue telemetry of output power.
Signal Type:	DEA
Range:	+30 dBm to Max Pout
Notes:	Type of info: peak detected output power: - ripple due to decay (at min PRF): <= 1% pp - Settling time from power application: <= 1 sec within 3% of final value

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Telemetry name:	BUS_CURR_TLM
Description:	Absorbed current from Tx_PWR line
Signal Type:	DEA
Range:	0 to 1A

Telemetry name:	TEMP_TLM
Description:	Hot spot temperature of TFE
Signal Type:	DEA
Range:	-30°C ÷ +80°C

Signal name:	SYNC
Description:	Synchronisation signal for the DC/DC converter
Signal Type:	DIF
Frequency:	131 KHz +/- 10%

TFE Power

Signal name:	PWR_AN
Description:	+ power line for TFE (live line + return)
Signal Type:	Power
Voltage:	Unregulated bus 21-36 V
Max Current:	18 W max (10 W no transmission, i.e. no input signal, TxRx on Rx, Tx gate OFF)

3.3.1.3 Internal Interfaces – TFE to ANT RTX Port

Signal name:	TFE_RTX
Description:	RF balanced connection to/from antenna (each connector carrying one polarity)
Connector type:	2 x TNC (balanced), female
Nominal impedance:	TFE output impedance shall maximise power transfer vs antenna load
Power level (Tx):	+40 (+/- 1.5) dBm
Max VSWR no damage (Tx/Rx):	Any phase

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3.3.1.4 Internal Interfaces – TFE to RX
RX Port

Signal name:	RX_RF
Description:	Received signal from TFE to Rx
Connector type:	SMA, female
Nominal impedance:	50 Ohm
Signal Type:	Linear frequency modulated (chirp) pulse
Centre frequency:	20 MHz
Signal bandwidth:	10 MHz
Pulsewidth:	85 msec, nominal
Notes:	Active switching performed within TFE. Power to TFE required to obtain a valid signal at RX input.

3.3.1.5 External Interfaces - Power

The power interface is constituted by two (primary and secondary) primary power lines at 22 to 36 V (28V nominal). The two lines corresponds to S/C sides A (primary) and B (secondary) and go directly to DES connectors, respectively, J06 and J07.

Inside the DES, the two primary power lines are OR-ed together and distributed to the users, RDS DC/DC and TFE. The latter is internally switched.

Interface design is such that only one of the two primary power lines shall be active at any time.

For power consumption, see section 3.6.1

3.3.1.6 External Interfaces – Thermal Control

The thermal control interface (which is physically implemented by the SEB J101 connector) is made by:

• two (primary and secondary) heater channels controlled by the S/C at a nominal voltage of 28V (22 to 36V), with a total heater resistance (for each channel) of 19 +/- 1 Ohm;

• four (with redounded connections) temperature sensors lines, 2 connected to the thermal reference point of the RDS and two to the TRP of the TFE, of type AD 590 (unconditioned).

•

3.3.1.7 External Interfaces - Command and Control

SHARAD receives commands frames from the S/C C&DH computer via a redundant LVDS interface. The nominal interface is associated to S/C Side A. The redundant interface is associated to Side B. Only one interface shall be active at any time. The Side_Select discrete signal provide indication about which interface is active at any time.

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Signal name:	CMD_Data
Description:	NRZ Command Data frame
Signal Type:	LVDS
Notes:	Data frames are multiple of 32-bits

Signal name:	CMD_Valid
Description:	Identification of a CMD_Data frame
Signal Type:	LVDS
Notes:	Signal active low when data are to be sampled

Signal name:	CMD_Clock
Description:	Clock signal to sample CMD_Data
Signal Type:	LVDS
Frequency:	515.625 Khz +/- 5%
Notes:	Sampling performed at negative-going edge.

Signal name:	Side_Select
Description:	Enables S/C selection of the Command Interface redundancy.
Signal Type:	OPTO
Control logic:	DES_CMD_SELECT High (LED On) => SIDE A Active – CMD I/F MAIN DES_CMD_SELECT Low (LED Off) => SIDE B Active – CMD I/F RED
Notes:	It is expected that side selection will be performed by S/C before SHARAD is switched on

Command protocol layering and frame layouts are provided in Section 4.

3.3.1.8 External Interfaces - Science Data

SHARAD sends telemetry packets (both Housekeeping and Science Data ones) to the S/C SSR via a hot-redundant LVDS interface. The nominal interfaces is associated to S/C Side

A. The redundant interface is associated to Side B. Both interfaces are active and the related data clock is generated since DES power on.

Signal name:	TLM_Data
Description:	NRZ Telemetry Data frame
Signal Type:	LVDS
Notes:	Data frames are multiple of 32-bits

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Signal name:	TLM_Valid
Description:	Identification of a TLM_Data frame
Signal Type:	LVDS
Notes:	Signal active low when data are to be sampled

Signal name:	TLM_Clock
Description:	Clock signal to sample TLM_Data
Signal Type:	LVDS
Frequency:	26.666667 Mhz +/- 5% (max. 30 MHz).
Notes:	Sampling performed at negative-going edge.

Telemetry protocol layering and frame layouts are provided in Section 4.

3.3.1.9 External Interfaces – Discretes

Discrete TMs
When the DES is switched off all signals are “high” (OC LED is Off).

Signal name:	SHR_Running
Description:	Provides indication that SHARAD is powered on and that the CPU is running.
Signal Type:	OPTO
Control logic:	OC ON = SHARAD Running, OC OFF = SHARAD Not Running
Notes:

Signal name:	SHR_Alive
Description:	Provides a pulsed indication that SHARAD software is running.
Signal Type:	OPTO
Control logic:	Not applicable
Timing:	The signal toggles state every 5 seconds.
Notes:	The signal starts toggling when DES enters Stand By state.

Signal name:	SHR_Operating
Description:	Provides indication that SHARAD is performing measurements.
Signal Type:	OPTO
Control logic:	OC ON = SHARAD Operating, OC OFF = SHARAD Not Operating
Notes:	The signal is active when DES leaves Stand By mode.

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Signal name:	SHR_Safe
Description:	Provides indication of a serious anomaly (like an Out Of Limit or a not-recoverable SW event).
Signal Type:	OPTO
Control logic:	OC ON = SHARAD in Safe/Idle, OC OFF = SHARAD Not in Safe/Idle
Notes:	The signal is active when DES goes into Safe/Idle State.

Note that the four TM discrete signals are used in a not conventional way during the Boot phase (which lasts about 28 seconds from Power On). During this phase the meaning of the signal is overridden and their status is used to provide indications of critical anomalies during execution of the Boot code.

Additional details are available in section 3.4.

Discrete TCs

Signal name:	TX_Enable
Description:	Driven by S/C to control the activation of SHARAD’s TFE
Signal Type:	OPTO
Control logic:	OC ON = TFE ON, OC OFF = TFE OFF
Notes:	For TFE control the signal is sampled at the transition from Warm Up 1 State to Warm Up 2 State.

Note that the TX_Enable signal has another role during the Boot process. At Power On Reset the signal is sampled and its status is used to select the active EEPROM from which the subsequent Boot phase will be executed. After the Power On Reset the signal resumes its conventional meaning.

Additional details are provided in section 3.4.

Signal name:	Time_Tic
Description:	Used by S/C to provide a timing reference after a TIME UPDATE Command.
Signal Type:	OPTO
Control logic:	The active edge is the positive going (rising) one.
Timing	- period is 1 second +/- 1msec - duty cycle is 50% +/- 10%. - maximum rise time is less than 50 nsec.
Notes:	See the synchronisation diagram below.

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Figure 3.3.1-4: DES OBT Synchronisation Timings

3.3.1.10 Connectors list
The following table provides basic details about SHARAD connectors.

Conn.	To	On	Type	No of pins	Used pins	Used for
J01	EGSE	DES	DBM-25S-NMB-1A7N	25	11	Slave DSP FIFO test connector
J02	S/C	DES	DBM-25S-NMB-1A7N	25	16	Nom. SDI, Nom. MCMD, MCMD_SEL
J03	S/C	DES	DBM-25S-NMB-1A7N	25	16	Red. SDI, Red. MCMD, Time_tick
J04	S/C	DES	DBM-25P-NMB-1A7N	25	10	Discrete_TM, Discrete-TC
J05	S/C	DES	DBM-25P-NMB-1A7N	25	21	Analogue monitors
J06	S/C	DES	DEM-9P-NMB-1A7N	9	5	RDS nominal primary power
J07	S/C	DES	DEM-9P-NMB-1A7N	9	5	RDS redundant primary power
J08	TX	DES	SMA RADIALL R125414001	1	1	DCG_out
J09	EGSE	DES	DAMA-15S	15	15	DCG test signals
J10	TX	DES	DEM-9S-NMB-1A7N	9	5	TXFE primary power
J11	EGSE	DES	DBM-25S-NMB-1A7N	25	21	EGSE test signals
J12	EMU	DES	DBM-25S-NMB-1A7N	25	18	DES status test signals
J13	EGSE	DES	DBM-25S-NMB-1A7N	25	23	Master DSP test connector
J101	SEB	SEB	DBM-25S-NMB-1A7N	25	12	SEB Thermal Control
J201	ANT	ANT
J202	ANT	ANT

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3.3.2	Mechanical Interfaces

SHARAD’s SEB is mounted, backward-looking, to the S/C engine deck by means of four M4 type screws (one for each "leg" of the SEB structure).

Four similar attachment points are used for each antenna hinge (8 total).

For a detail of the SHARAD to MRO mechanical interface, refer to MICD available in [RD14].

3.3.3 Thermal Interfaces

SHARAD elements are thermally decoupled from the Spacecraft and have autonomous thermal control devices managed by S/C.

Both the SEB and the Antenna are mounted on the MRO engine deck using thermal insulating washers to prevent heat exchange with the spacecraft.

SEB thermal control is then achieved by means of:

• radiative exchange: the outer side of the SEB structure is partially painted with white paint (with high emissivity in the infrared region) to provide a radiative exchange path to the space in order to dissipate the heat produced during operation. The rest of the SEB is covered by a thermal blanket for insulation purpose.

• survival heaters: to prevent the SEB from going at too low temperature when in OFF mode, two series of heaters (primary and redundant) can be switched by the spacecraft according to the readings of four active temperature sensors (AD590) placed near the temperature reference points of the RDS and TFE.

The thermal control of the antenna (which does not dissipate significant amounts of heat during operation) is instead passive, with the exception of the release actuator mechanism. Heaters are located on the S/C panel below the antenna and are used to increase the temperature of the antenna hinges within the temperature operating range of the deployment actuators. They are used only before the antenna deployment.

The stowed antenna is surrounded by a Germanium-Kapton thermal shield, which has the main purpose to prevent overheating during the aerobraking phase.

3.4.1 SW Architecture

3.4.1.1 SW Overall Design

SHARAD SW requirements are mapped in the following Use Cases diagram, while Figure 3.4.1-2 shows DES SW decomposition in components/modules.

Figure 3.4.1-1: DES SW Use Cases

All components/modules are implemented over the Virtuoso Real-Time Executive, but for the Boot (or Boot/Loader) module, which is a stand-alone application written only in assembly language. All other components/modules are written mainly in C Language, while many HW interfaces are written ADSP21020 assembly language.

Ten different blocks are depicted, some of them can be logically grouped in two macro modules:

• The Command and Control module, which is in charge of managing the System and its interfaces with spacecraft. It is composed by:

1. o Command Handler

2. o Telemetry Handler

3. o Mode Transition Handler

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1. o Built in Test

2. o Boot functionalities

3. o Background auxiliary activities (like Watchdog reset)

4. o Discrete Telemetry lines functionalities

• The Radar Sequencer, which includes:

1. o Parameter Table access functionalities

2. o Radar HW programming

3. o Basic Data Processing, using polynomial interpolation of Mars surface as defined by [AD2]

4. o Tracking processing, implementing tracking algorithm as defined by [AD2]

Additional descriptions to be provided in next issue.

Figure 3.4.1-1: DES SW Components

Software processes running in DES SW are listed as instanced OS modules tasks in the following table:

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Module	Process Name
TLM_HANDLER	TM_Science_Creator TM_HK_TLM_CMD_Task TM_HK_TLM_ENG_Task TM_end_DMA_hdl_Task TM_Send TIMEOUTs_Handler
CMD_Handler	TC_Validation TC_Exec_Handler TC_Reception Suspend_TC_Reception
OST & PRI Management	PRI_Handler
BUILT IN TEST	BIT_Handler
Transition Handler	Transition_Handler
Background	Background

3.4.1.2 SW Release History
The following releases have been used for the development of SHARAD EM:

Rel. 1.1	First formal release.
Rel. 1.2	Used to support functional tests in LABEN.
Rel. 1.3	Used to support instrument integration tests in ALS.
Rel. 1.4	Delivered for integration in the OTB.

The following releases have been developed for SHARAD PFM: Rel. 2.1 Derived from 1.4, including post OTB integration changes and new

configuration changes. Rel. 2.2 Used to support DES Functional and Environmental tests in LABEN Rel. 2.3 Installed in DES PFM for SHARAD integration testing in Alenia (Tracking

module present but not operational, dummy data only).

Rel. 2.4 Software qualification release (full Tracking Module capability and rel. 2.3 SPR’s resolution) installed on PFM for delivery. This SW release has also been retrofitted to the EM in the OTB.

Rel. 2.5 Future release, if required. A formal declaration of the release status is available in [RD-13].

3.4.2 HW/SW Interfaces

Not considering DSP CPU internal configuration registers, the DES architecture contains a number of configuration registers implemented in the three FPGA used in the design. These are called DES Internal Registers and are accessed (read-only, write-only or read-write) as memory mapped registers through the DES system bus.

The DCG offers a series of internal registers used to store its operating parameters. Some of these parameters are set at startup, others are re-programmed during the PRI cycles. These

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are called DCG Registers and are accessed (write-only) by means of the serial DCG memory load interface.

3.4.3 Memory allocation

The DSP on board of DES has an Harvard architecture, that means that two indipendent memory spaces are implemented, as shown in Figure 3.4.4-1:

• The Program Memory, divided into program EEPROM and program RAM

• The Data memory

EEPROM memory is hardware partitioned in two 64 Kword banks, or Partitions, (by toggling the highest order address bit of the EEPROM chips). This arrangement has been required to increase the redundancy of Boot/Loader code. The resultant organisation of EEPROM banks is shown in Figure 3.4.3-2.

Selection of EEPROM is performed by means of the TX_ENABLE discrete TC signal. The signal is sampled at Power On Reset and its status, latched in a FPGA register, is used to determine the active EEPROM partition. There exist a SW capability to alter the status of the controlling bit thus implementing access to the not active partition for particular purposes (EEPROM Patch/Dump or EEPROM Re-write function).

According to Flight Rules, a nominal boot requires the TX_ENABLE signal to be not active (to prevent accidental TFE activation). The following definitions therefore apply:

• Nominal Boot: EEPROM Partition A

• Alternate Boot : EEPROM Partition B

Additional details on the management of the two memory partitions are given in the following paragraphs.

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Figure 3.4.3-1: DES Memory Organisation.

Figure 3.4.3-2: DES EEPROM Memory Organisation.

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3.4.3.1 Program Memory Map
The following table summarizes the 48-bit wide Program Memory addressing space map.

Type and location size	Address
	Start	End	Description	Patchable?
	0x00000000	0x000018FE	Boot Sector	N
	0x000018FF	0X000018FF	Boot crc	N
	0x00001900	0x00003FFE	Init Sector	Y
EEPROM “A”	0x00003FFF	0x00003FFF	Init crc	Y
48bit	0x00004000	0x0000DFFE	DES SW Image	Y
	0x0000DFFF	0x0000DFFF	DES SW crc	Y
	0x0000E000	0x0000EFFF	PT Defaults	Y
	0x0000F000	0x0000FFFF	Boot Copy (part 1)	N
	0x00010000	0x000118FE	Boot Sector	N
	0x000118FF	0X000118FF	Boot crc	N
	0x00011900	0x00013FFE	Init Sector	Y
EEPROM “B”	0x00013FFF	0x00013FFF	Init crc	Y
48bit	0x00014000	0x0001DFFE	DES SW Image	Y
	0x0001DFFF	0x0001DFFF	DES SW crc	Y
	0x0001E000	0x0001EFFF	PT Defaults	Y
	0x0001F000	0x0001FFFF	Boot Copy (part 2)	N
Static RAM 48bit	0x00020000	0x000200FF	RTOS reserved	Y
	0x00020100	0x00029FFF	DES SW (runtime)	Y
	0x0002A000	0x0009FFFF	DES SW Program data	Y

Note that the first three sectors of the EEPROM include a dedicated checksum for the given

section. The checksum value is used to verify memory integrity during Boot and BIT phases. All the CRC sectors (i.e. Boot, Init and DES SW) store their checksum values in the following format:

0x0000CCCC0000 where CCCC is the relevant checksum value.

EEPROM Boot Sector
The Boot Sector contains minimal, highly optimized code to perform:

• integrity tests
  

• dedicated CMDs reception in order to reload code during power on phase
  

• HW setup routines
  

• RTOS setup routines
  The interrupt vector table is also contained in this sector.
  

The Boot Sector is write protected by SW, i.e. a Patch CMD at location between 0x00000000
and 0x000018FF (or 0x00010000 and 0x000118FF for partition “B”) is always rejected. The
only way the SW can write into boot sector is by means of the EEPROM Rewrite CMD.

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EEPROM Init Sector

The Init Sector acts as a kind of bridge between boot code and real application SW. It contains a SW “bridge” to remap the interrupt vector table from EEPROM to RAM and RTOS runtime libraries (such as mathematical libraries for floating point operations, FFTs, etc.).

EEPROM DES SW Image

The DES SW Image is the copy of the application SW (as well as that of some required variables). This image is copied into RAM during RTOS initialization.

EEPROM Parameter Table Defaults

The Parameter Table Defaults Sector contains a partial copy of the PT that is to be stored in RAM during DES SW start-up. DES SW uses only the PT copied in RAM for its operations.

The PT Image stored in EEPROM contains all the PT values (starting from 0) excluding the 4096 complex points of the reference function used by the tracking algorithm (these values are generated at runtime generated during DES SW start-up, either at Power On or in case of warm restart).

EEPROM Boot Sector Copy

The last segment of each EEPROM partition contains a partial copy (roughly half) of the Boot Sector. The two portions can be assembled together to obtain a complete copy of the Boot Sector (the B part shall be appended to the A part).

This copy of the Boot Sector is used for the automatic recovery of unexpected corruptions of Boot Sector due to external causes (like SEUs or component failures). See EEPROM Rewrite in next paragraph for further details.

RAM

The Program RAM mainly contains the runtime DES SW Image copied from the EEPROM and some data structure used by the RTOS.

3.4.3.2 Data Memory Map

The following table summarizes the 32-bit wide Data Memory addressing space map.

Type and location size	Address
	Start	End	Description	Patchable?
	0x00000000	0x000011FF	RTOS reserved	Y
Data RAM	0x00001200	0X00025FFF	DES SW data	Y
32bit	0x00026000	0X0002CFFF	Parameter Table	Y
	0x0002D000	0X0007FFFF	RTOS reserved	Y

Data RAM is a 32bit addressable space that contains:

• RTOS data structure (for instance: stack and heap segment, system variables etc.);

• DES SW variables;

• Runtime Parameter Table.

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3.4.4	Memory Management

3.4.4.1 Patch and Dump operations

DES memories can be patched and dumped by means of dedicated Comands (PATCH_MEMORY and DUMP_MEMORY).

Patches operations are permitted for all memory addressing ranges excepting the critical areas of the Boot Sectors and the Boot Sector Copies.

Tables in paragraphs 3.4.3.1 and 3.4.3.2 show the patchable addressing ranges.

Dump operations are allowed for all memory addressing ranges, even including not existing locations. This feature has been inserted in order to obtain system flexibility. A dump from a not existent location will yield 0xFFFFFFFF (or 0xFFFFFFFFFFFF) value for the addressed location.

3.4.4.2 Full SW re-load

The Boot/Loader code provides the capability to perform a full SW re-load by providing a complete, contiguous, image of the Init, DES SW Image and PT Defaults EEPROM sectors.

This capability is exercised by sending a LOAD_REQUEST command to the DES during a 15 seconds window marked by the SHR_Alive signal being low during the Boot phase.

When the command is received, the Loader is activated and, without further timing criticalities, LOAD_DATA commands can be sent to compose the whole image.

The new image loading ends with a LOAD_CHECKSUM command which provide a checksum value for the entire image (sector checksums are embedded in the image data). After this command is received the Loader copies the image (temporarily stored in RAM) into the active EEPROM partition and a full re-start from EEPROM is performed.

Additional details will be provided in next issue.

3.4.4.3 EEPROM Re-write function

The EEPROM Rewrite function (activated with the RESTART EEPROM Re-write Command) performs a refresh of all DES EEPROM locations, including the Boot Sectors.

This feature has been implemented due to an issue concerning a bit toggling detected on the same EEPROM component on board a previous NASA mission. Reasons for this issue are still under investigation. For safety purposes, a system to recover an EEPROM corruption, based on the Majority Voting algorithm, as therefore been implemented in SHARAD’s DES.

The EEPROM Re-write, originally meant to be periodically run as a background task, as been assigned a dedicated command for “manual” execution due to the extremely criticality of its operations (so critical that during the function, all the DES nominal operations are suspended).

The EEPROM Re-Write function is activated by the RESTART EEPROM Re-Write command, which includes selection of the EEPROM partition to be targeted. The following steps are then performed:

1. The EEPROM TOGGLE register is saved in order to recover nominal operation at the end of sequence.

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2. For each memory segment on the selected partition, the following operation are performed:

1. All interrupts are disabled to put the RTOS kernel in a freeze state and to ensure that any task cannot interfere with the re-write operations. Note that this also implies that the SHR_Alive TM signal will stop toggling.

2. EEPROM is put in Write enable condition.

1. For each location of the segment:

2. A. The location is read.
3. B. The location is written with value previously read.
3. The EEPROM is put back in Write protected condition.

1. Interrupts are re-enabled, the RTOS awakes and ALIVE signal returns to toggle.

2. In case the re-write is concerning the Boot Sector, then the following extra actions are performed:

1. For each location in the boot sector:

A. The location is read and stored apart

B. The corresponding location in the other partition is read and stored apart

C. The corresponding location in the Boot Copy Sector is read and stored apart

D. Let’s call the three values A, B and C. These values are compared according with the following algorithm (expressed in pseudo-code):

if (A <> B) then
if (A = C) then
recover location B
else if (B = C)
recover location A

else
// all three location are different
do nothing

else if (B <> C) then
recover location C

where the operation “Recover location x” consists in the following steps:

1. Enable EEPROM writing

2. Disable interrupts

3. Write corrupted location with the contents of the other two not corrupted location

4. Disable EEPROM writing

5. Re-enable interrupts

5. At the end of the Rewrite sequence, the starting partition is retrieved.

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3.4.5 Boot Sequence

3.4.5.2 Not Nominal Boot

The following table shows TM discrete signals and DES SW status after Power On:

Condition		Discrete Telemetries			SW Status
	Running	Alive	Safe	Operating
Nominal condition	ON	Toggling	OFF	OFF	Running
Boot CRC error	OFF	OFF	ON	OFF	Idling
Init CRC error	OFF	OFF	ON	OFF	Idling
DES SW CRC error	OFF	OFF	ON	OFF	Idling
DES RAM Errors	OFF	OFF	ON	ON	Idling

Note that in the column SW Status, the label “Idling” identifies an internal DSP condition (which means that SW is altogether stopped). This is not to be confused with the Safe/Idle State.

Although different error conditions have the same TM status, it is underlined that they are presented in different time. Analysis of a not nominal boot condition shall consider that:

• Boot CRC and Init CRC errors appears after a few seconds from Power On

• SW CRC error appears only after the end of the 15 seconds SW re-load window

Figure 3.4.5-1 shows the behavior, as seen on J04 connector, of TM discrete signals during a nominal Boot. Note that signals are used with negative logic (i.e., active low).

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Figure 3.4.5-1: Nominal Boot TM Discrete Signals Behavior.

3.4.6 Time Management

SHARAD’s DES implements two different counters to keep track of time:

• the On Board Time (OBT) Counter.

• the High Resolution Time (HRT) Counter;
  The clock for both counters is necessarily derived from the 80 MHz TCXO Master Oscillator.
  

3.4.7 Monitoring

The DES monitors eight analogue channels assigned as follows:

These channels are acquired as 8 bit values and are HW sampled every second. Values are stored dedicated registers and are reported in HK Engineering telemetry as raw values.

DES Monitoring is managed by a OS task which starts its operations when the DES enters in STANDBY State. Within this task, channels are periodically checked for out of range condition. The checking period is defined by a PT value (PT_MON_SAMPLE).

For a given channel N, its value is verified against two limits assigned to the channel: PT_CHn_ULIM (Upper Limit) and PT_CHn_LLIM (Lower Limit). If an Out Of Limits (OOL) is found for three consecutive times on the same channel, then an Out Of Limits SW event condition is generated, which produces:

• A HK Log telemetry indicating the out of range channel and its value.

• A transition to SAFE/IDLE State.

The Upper and Lower Limit for all channels are stored in Parameter Table.

Note that the Out of limit test is not inclusive, e.g. a channel is in out of range when its value is greater than parameter, not greater or equal the parameter.

Monitoring of RX and TFE parameters is subject to the condition that those units are switched on (because the temperature sensors are active, AD590 type, ones). Therefore, when the DES is in State for which the RX and/or the TFE are switched off, related channels are not monitored and are reported with a 0x00 value in HK Engineering telemetry.

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When running, the monitoring task is always active, there being no command to disable it. In case it were necessary to disable the monitoring of a given channel, it is possible to alter the corresponding Out Of Limits values in Parameter Table in such a way that any measured value cannot produce an OOL condition. To achieve this result it is sufficient to set the relevant PT_CHn_ULIM paramter value to 0xFF and “the PT_CHn_LLIM value to 0x00 (where n is 1 to 8 according to the given channel).

3.4.8 Built In Test

The DES SW implements a Built In Test feature to periodically verify DES memory integrity. The BIT is awaken every hour (3600 s) and it calculates checksums for the following memory segments:

• Boot sector of EEPROM partition in use

• Init sector of EEPROM partition in use

• DES SW Image of EEPROM partition in use

• Program RAM

• Each computed checksum is verified with the corresponding value stored with the relevant segment. If a mismatch is found:
• a HK Log telemetry will report the identification of the corrupted segment, and the computed and expected checksum values;

• a transition to SAFE/IDLE mode will be performed.

The BIT is executed for the first time immediately after RTOS initialization, that is at the end of the CHECK/INIT State.

Although the BIT is always running (even during DES operative modes) it is spawned by RTOS as a very low priority task in order to avoid interferences with other DES operations.

3.5.1 Instrument States/Modes

The DES, and SHARAD, perform different tasks within their operational sequence, such as power-up, initialisation, transmission and science operations. Consequently different states (and modes) can be identified.

Power Off

Power Off

Operational Modes

Note: The first transition to an Operational Mode (from Warm Up 2 Act.) is performed when the OST Time Tag expires and OST processing begins. The transition back to Warm Up 2 (Deac.) is performed when OST processing ends.

Figure 3.5-1: States/Modes Diagram

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The following definitions apply:

• A "State" is considered as a specific configuration of the hardware and software used to perform a specific task.

• An “operating mission mode” (or “Mode”) is considered as one of the specific mission task required by the mission as store data or downlink data. Mode availability depends on States.

The Boot Sequence is not considered as a State but a transitory condition between Power Off State and Check/Init State. See Check/Init State for more details.

3.5.1.1 Power Off State

In Power Off State, the DES is not powered. The DES can be made to transition to Power Off State, by switching it off, while being in any other State/Mode.

3.5.1.2 Check/Init State

Check/Init State is nominally entered, after applying power to the DES, at the end of the Boot Sequence which loads the main SHARAD SW code into RAM. In case of an unsuccessful Boot Sequence, a Boot Report is generated using the appropriate telemetry format.

This State may be also entered as result of some applications of the RESTART Command.

While in this State, the HW and SW initialisation of the DES is performed and commands cannot be received, neither Science Data nor Telemetry are generated and monitoring is not performed.

In this State the RX and the TFE are OFF.

At the end of a successful initialisation this State is automatically exited with a transition to Stand By State. In case of errors, this State is exited with an automatic transition to Safe/Idle State.

3.5.1.3 Stand By State

Stand By State is automatically entered as result of a successful DES initialisation or at the end of the processing of an Operational Sequence Table. While in this State, the DES receives and interprets Commands, generates housekeeping Telemetry and monitoring is enabled. No Science Data are generated.

In this State the RX and the TFE are OFF.

This State is nominally exited after reception of a valid ENABLE OST Command, which starts the processing of the Operational Sequence Table, switches ON the RX and performs an autonomous transition to Warm Up 1 State.

In case of errors or anomalies, excluding the reception of incomprehensible or invalid Commands but including the detection of an out of limits condition for monitored parameter, a transition is performed to Safe/Idle State.

3.5.1.4 Warm Up 1 State - activation

Warm Up 1 State is automatically entered as a first preliminary step toward the execution of an Operational Sequence Table.

In this State the RX is switched ON and a warm up delay is waited. The TFE is, and remains, OFF.

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Reception of Commands is disabled, and any Command received while in this State shall be logged and discarded. Telemetry is generated and monitoring is active. No Science Data are generated.

This State is nominally exited, at the end of the RX Power Up (or Activation) Delay, by switching ON the TFE and autonomously transitioning to Warm Up 2 State.

The actual switching ON of the transmitter depends on the state of the TX_ENABLE signal (DES_TC_1). If the signal is not active at the beginning of the state transition, the transmitter will not be switched ON but the rest of the State behaviour shall not be altered.

In case of an anomaly, that is the detection of out of limits condition for monitored parameters, a transition is performed to Safe/Idle State thus ending the processing of the OST.

3.5.1.5 Warm Up 2 State - activation

Warm Up 2 State is automatically entered as a second preliminary step in the execution of an Operational Sequence Table.

In this State the RX and the TFE are switched ON and a warm up delay is waited.

Reception of Commands is disabled, and any Command received while in this State shall be logged and discarded. Telemetry is generated and monitoring is active. No Science Data are generated.

At the end of the TFE Power Up (or Activation) Delay the DES remains idling, waiting for the expiration of the OST Time Tag (which marks the beginning of the first operational mode programmed into the Table). Therefore, this State is nominally exited, as soon as the OST Time Tag expires, with an autonomous transition to the Mode specified by the first OST entry.

In case of an anomaly, that is the detection of out of limits condition for monitored parameters, a transition is performed to Safe/Idle State thus ending the processing of the OST. If the OST Time Tag is already expired at the end of the TFE delay a transition back to Warm Up 1, and then to Stand By, is performed.

3.5.1.6 Safe/Idle State

Safe/Idle State is automatically entered whenever a not nominal condition is encountered in any other State/Mode. In this State the RX and the TFE, if ON, are switched immediately OFF at the end of the transition.

In Safe/Idle the DES is able to receive and interpret a limited set of Commands including PATCH_MEMORY, DUMP_MEMORY and RESTART. Telemetry is generated and monitoring is active. No Science Data are generated.

The State is exited by an explicit Power OFF, performed by S/C, or by means of a RESTART Command. In the latter case the exit will produce a transition to the Check/Init State (with the software restarted directly from RAM or fully re-loaded from EEPROM).

3.5.1.7 Warm Up 2 State - deactivation

Warm Up 2 State is automatically re-entered at the end of the execution of the last entry of the Operational Sequence Table. In this State the RX and the TFE are, and remains, ON, while a brief TFE Power Off (or De-Activation) Delay is waited.

Reception of Commands is disabled, and any Command received while in this State shall be logged and discarded. Telemetry is generated and monitoring is active. No Science Data are generated.

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This State is nominally exited, at the end of the Power Off Delay, by switching OFF the TFE and autonomously transitioning back to Warm Up 1 State.

In case of an anomaly, that is the detection of out of limits condition for monitored parameters, a transition is performed to Safe/Idle State.

3.5.1.8 Warm Up 1 State - deactivation

Warm Up 1 State is automatically entered after Warm Up 2, during the deactivation process after the end of the processing of an Operational Sequence Table. In this State the TFE is OFF and the RX is ON and remains, ON, while a brief RX Power Off (or De-Activation) Delay is waited.

Reception of Commands is disabled, and any Command received while in this State shall be logged and discarded. Telemetry is generated and monitoring is active. No Science Data are generated.

This State is nominally exited, at the end of the power off delay, by switching OFF the RX and autonomously transitioning back to Stand By State.

In case of an anomaly, that is the detection of out of limits condition for monitored parameters, a transition is performed to Safe/Idle State.

3.5.1.9 Operational Modes

Operational modes nominally see SHARAD configured with both the TFE and the RX switched ON regardless of the modes to be executed. However, if while transitioning through Warm Up 1 – Activation, the TX_ENABLE (DES_TC_1) was not active, then the TFE will not be switched ON. In this not nominal condition (used only for safe testing of the instrument) all operational modes are executed nominally.

Operational (or Measurement) Modes corresponds to the different actions that the DES may perform under the guidance of OST entries. Each OST entry specifies details for the transition to, and the execution of, a given Operational Mode. After the last Mode a transition is automatically performed to Warm Up 2 State.

Telemetry is always be generated during Operational Modes and monitoring is active. Commanding of the instrument is disabled and the DES will report a software anomaly in case commanding is attempted, without interrupting the OST processing.

In case of other error or anomalies during Operational Modes processing, an automatic transition is performed to Safe/Idle State.

Subsurface Sounding (SS) Mode

Subsurface Sounding Mode is the main measurement mode for SHARAD. In this Mode the DES shall perform scientific measurements by transmitting radar pulses and collecting, processing and formatting received echoes. PRI and duration are variable depending on parameters specified in each OST entry. A variable Science Data rate will be produced in this Mode depending on the specific processing parameters.

Receive Only (Rcv Only) Mode

Receive Only Mode is used to perform passive measurements mainly during the on-orbit phase, but can also be used to check the performances of the instrument during the cruise phase (even with the antenna folded). The TFE is ON but no transmissions will be performed. A variable Science Data rate will be produced in this Mode depending on the specific processing parameters.

Calibration (Calib) Mode Calibration Mode is used to perform instrument calibrations during the on-orbit phase. A variable Science Data rate will be produced in this Mode depending on the specific processing parameters.

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Wait Mode

Wait Mode is an idle mode used to introduce gaps in the measurement phase of an active orbit. Both the RX and the TFE are ON but no transmissions will be performed. No Science Data will be produced.

Test Mode

Test Mode is a debug mode used to generate a stream of science data simulating an instrument operational mode exercising all DES internal functions. A static pattern of data is also generated occasionally. Both the RX and the TFE are ON.

In current SW release (2.4) the Test Mode perform an SS Mode and therefore the TFE will transmit radar pulses. A future SW release may request to change this behaviour in order to have the Test Mode perform a RO Mode thus permitting to switch on the TFE without any danger in case the antenna has not yet been deployed.

3.5.1.10 States/Modes Indentification

DES States/Modes are identified by a unique numerical code, and are reported in every HK telemetry packet. The following table shows relevant identification values:

Sharad Mode	ID
CHECK/INIT	0x0
STANDBY	0x1
WARMUP1 Activation	0x2
WARMUP2 Activation	0x3
IDLE	0x4
SS	0x5
RECEIVE ONLY	0x6
WAIT	0x7
CALIBRATION	0x8
WARMUP1 Deactivation	0x9
WARMUP2 Deactivation	0xA
TEST	0xB

3.5.1.11 Allowed Transitions

The following table shows DES allowed mode transition (blank cells means transition not allowed):

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						Final State/Mode
		CHECK / INIT	STAND BY	WU1 ACT	WU2 ACT	SAFE/ IDLE	SS	REC ONLY	WAIT	CALIB	TEST	WU1 DEA	WU2 DEA
Start State/Mode	CHECK /INIT	YES	YES			YES
	STANDBY	YES	YES	YES		YES
	WM1ACT			YES	YES	YES
	WM2ACT				YES	YES	YES	YES	YES	YES	YES		YES
	SAFE/IDLE	YES				YES
	SS					YES	YES	YES	YES	YES	YES		YES
	REC_ONLY					YES	YES	YES	YES	YES	YES		YES
	WAIT					YES	YES	YES	YES	YES	YES		YES
	CALIB					YES	YES	YES	YES	YES	YES		YES
	WM1DEA		YES			YES						YES
	WM2DEA					YES						YES	YES
	TEST					YES	YES	YES	YES	YES	YES		YES

Note that a transition to the same mode is always allowed.

The SAFE/IDLE State is a safety state that is entered whenever an unexpected event occurs
or a potentially dangerous situation is detected.
There are four conditions that can force the DES into SAFE/IDLE State:

• On Monitoring OOL event occurrence;

• On Built In Test (BIT) failure;

• On certain Time Update failures;

• When an OST is found corrupted before starting science operations.