Time Line

•1516.783 (S/C time 900374596.779) –EGA commanded ON, EGA Heater goes ON

•1518.000 –TEFSW receives corrupt engineering packet

•1520.004 –EGA heater goes OFF

•1535.733 –First EGA Boot Message

•1578.033 –TEGA reports successful EGA startup

19 minutes later

•2718.226 –EGA receives first power down command from our block

•2743.212 –sci_fltpthissues TEGA shutdown

Corrupt Engineering Packet

•TEFSW does not check packet checksum

•Packet flagged with a checksum error on the ground

•Inspection of packet shows a normal 514 byte engineering packet,BUT

•The last 6 bytes were replaced by the VML_SET packet containing the GV_TEGA_EGA_ABOVE_MIN_OP_TEMP = 1 global variable command

6 Byte VML_SET packet

Corrupt Engineering Packet

How Can This Be?

•S/C communication hardware and software inherited from Odyssey GRS

–TEGA has 2 S/C transmit buffers, and many packet assembly buffers

–When a packet is fully assembled in one of the packet buffers a flag is set

–Background loop sees the flag, checks for available S/C buffer

•If no buffer available, do nothing

–If buffer is available, packet is copied into buffer and buffer is marked BUSY

•If transmitter is not busy, initiate buffer transmission

•If transmitter is busy, do nothing

Meanwhile, in hardware land…

•DMA unit sends interrupt to 386 FSW when transmitter goes not busy

–If there is data in a S/C buffer, 386 FSW sets a byte counter inthe DMA unit

–DMA unit goes busy and starts sending bytes from the buffer to the S/C

Possible Failure Mechanisms

•386 FSW “forgets”that the engineering packet is being transmitted

–Copies the VML_SET packet into the buffer while it is being transmitted

•FPGA “forgets”which buffer is being transmitted

–Starts sending data from the other buffer before finishing the current buffer

•TEFSW is reading bytes out of the PACI

–VML_SET packet arrives and somehow overwrites end of engineeringpacket